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BIT1612 10-Bit Digital Video Decoder with OSD and T-CON
20
6.12 TCON Function
BIT1612 內建 Programmable TCON Function 將可經由 BIT1612 直接驅動 Analog Interface Panels，其相關
Registers 設定請參考下表。
Table 6-15 TCON Function Register
Mnemonic Address R/W Bits Description Default
R_STH_START
0x023[6:4],
0x021[7:0]
RW 11 STH Signal Start 0x025
R_STH_END
0x023[2:0],
0x022[7:0]
RW 11 STH Signal End 0x026
R_LD_START
0x026[6:4],
0x024[7:0]
RW 11 LD Signal Start 0x001
R_LD_END
0x026[2:0],
0x025[7:0]
RW 11 LD Signal End 0x037
R_CKV_START
0x029[6:4],
0x027[7:0]
RW 11 CKV Signal Start 0x027
R_CKV_END
0x029[2:0],
0x028[7:0]
RW 11 CKV Signal End 0x051
R_OEH_START
0x02C[6:4],
0x02A[7:0]
RW 11 OEH Signal Start 0x014
R_OEH_END
0x02C[2:0],
0x02B[7:0]
RW 11 OEH Signal End 0x015
R_VCOM_SHIFT
0x030[6:4],
0x02D[7:0]
RW 11 VCOM Shift 0x014
R_STV_START
0x030[3:2],
0x02E[7:0]
RW 10 STV Signal Start 0x003
R_STV_END
0x030[1:0],
0x02F[7:0]
RW 10 STV Signal End 0x004
R_POL_CKV 0x031[0] RW 1 CKV Output Polarity 0
R_POL_STV 0x031[1] RW 1 STV Output Polarity 0
R_POL_STH 0x031[2] RW 1 STH Output Polarity 0
R_POL_LD 0x031[3] RW 1 LD Output Polarity 0
R_POL_FRP 0x031[4] RW 1 FRP Output Polarity 0
OEH Output Polarity
0: Normal
R_POL_OEH 0x031[5] RW 1
1: Invert
1
OEH gated with output data enable
0: Disable
R_OEH_GATE 0x031[6] RW 1
1: Enable
0
TCON Function Enable
0: Disable
R_TCON_EN 0x031[7] RW 1
1: Enable
1
STV Output Selection
0: STV1 = OUT, STV2= IN
R_STV_SEL 0x032[0] RW 1
1: STV1 = IN, STV2 = OUT
0
STH Output Selection
0: STH1 = OUT, STH2= IN
R_STH_SEL 0x032[1] RW 1
1: STH1 = IN, STH2 = OUT
1
TCON U/D Signal
0: Low Level
R_TCON_UD 0x032[2] RW 1
1: High Level
0
TCON R/L Signal
0: Low Level
R_TCON_RL 0x032[3] RW 1
1: High Level
1
Q2H Output Polarity R_POL_Q2H 0x032[4] RW 1
0: Normal
0
- BIT1612 1
- Content 2
- 1 General Description 11
- 2 Features 11
- 3 Order Information 13
- 4 Block Diagram 13
- 5 Pin Definition 14
- 6 Functional Description 18
- 6.4 Pad Type Setup 22
- 6.6 System Enable and Reset 23
- 6.7 Clock Domain Systems 24
- Panel Active Window 26
- Blank Range 26
- HSYNC Output 26
- VSYNC Output 26
- 6.9 Output Data Path 27
- 6.10 Special Output Setup 28
- Input VSYNC 29
- Output VSYNC 29
- 6.12 TCON Function 30
- 6.15 Background 2 33
- 6.17 Auto Blank Screen 34
- Input Image Window 35
- HSYNC Input 35
- VSYNC Input 35
- (Internal VD) 36
- R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 37
- G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 37
- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 37
- 6.20.7 RGB565 38
- 6.21 Input Mode Selection 39
- Background 41
- 6.24 Scaling Engine 42
- 6.25 Timing Adjustment 45
- Pre-Image Enhancement 46
- Post-Image Enhancement 46
- 6.26.3 Sharpness Process 47
- 6.26.7 LUT Gamma Correction 48
- 6.26.8 Dither 48
- Factor 0x80 49
- 6.27 PWM Function 50
- R_PWM_REF 51
- Base on panel clock 51
- R_PWM_FREQ 51
- R_PWM_DUTY 51
- Base on reference clock 51
- 6.28.5 VBI Data Slicer 55
- 6.28.6 Source Detection 55
- 6.28.7 Luminance Process 56
- 6.28.8 Chroma Process 57
- 6.28.9 Comb Filter Process 58
- 6.28.10 AGC and ACC Process 60
- 6.28.11 AFE and PLL Control 63
- 6.30 Serial RGB Output 68
- 6.31 BIT1690 Interface 68
- 6.32 OSD Function 69
- 6.32.2 OSD Memory Mapping 70
- R_Wx_INDEXS 71
- R_Wx_INDEXE 71
- R_BANK_SEL = 000 72
- If Display RAM 72
- {0x503[4],0x403[6:0]} = 72
- {0x501[4],0x401[6:0]} 73
- R_Wx_INDEX_S 76
- R_OSD_LAYER[2:0] = 001 77
- 6.32.7 OSD Clock Control 79
- 6.33 Timer 80
- 6.34 IR Decoder Function 81
- 6.35 GPI and KEY Function 82
- 6.36 PLL and OSC Pads 82
- 6.37 Auto Detection 83
- 01: From VSYNC1 Pin 85
- 10: From HSYNC2 Pin 85
- 11: From VSYNC2 Pin 85
- 7 User Interface 86
- 7.2.1 Architecture 89
- 7.2.2 Instruction Set 91
- 7.2.3 Start and Interrupt 94
- 7.2.6 Watch Dog Timer 95
- 7.2.8 TWSI Write/Read 96
- 7.2.9 SPI Interface 96
- 7.2.10 Debug Mode 96
- 7.3 Slave Mode 97
- 7.3.2 TWSI Protocol 98
- From Pin 104 Setting 100
- From Pin 105 Setting 100
- 8 Timing Diagram 101
- 9 Electrical Characteristic 103
- 10 Soldering Information 104
- 11 Package Information 105
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